1. Field of the Invention
The present invention relates to the field of semiconductor fabrication and more particularly to method of increasing circuit density by providing a discontinuous source/drain structure.
2. Description of the Relevant Art
In the conventional fabrication of an MOS integrated circuit, a silicon wafer is divided into a plurality of active regions and field regions typically through the use of a selective oxidation or trench formation process during which dielectric isolation structures are fabricated into the field regions of the substrate to provide physical and electrical isolation between adjacent, subsequently formed transistors comprising the integrated circuit. In this manner, the semiconductor substrate is essentially divided into active regions and field regions. The field regions in the conventional process flow are characterized by an isolation dielectric structure fabricated into the upper surface of the silicon substrate. The presence of these dielectric isolation structures is required in the conventional integrated circuit process to prevent a conductive path from being formed between each active area of the transistor during a subsequent source/drain implant. Typically, a source/drain implant in a conventional semiconductor process is performed across the entire surface of the substrate. The presence of patterned polysilicon gate structures on the wafer during the source/drain implant results in the formation of MOS transistors. But for the presence of the isolation structures, however, each of the source/drain regions created by the source/drain implant would be electrically coupled.
Dielectric isolation structures are typically fabricated with a LOCOS process or with shallow trench isolation structures. In a LOCOS process, the field regions of the silicon substrate are thermally oxidized by patterning a silicon nitride layer over the active regions of the substrate, and thereafter, thermally oxidizing the exposed portions of the substrate to create relatively thick dielectric structures over the field regions of the wafer. In addition to requiring a photolithography step, LOCOS processing typically requires the deposition of a pad oxide layer prior to the deposition of a silicon nitride layer and further requires a rather extensive thermal oxidation step to produce an oxide thickness necessary to isolate adjacent structures. Similarly, a shallow trench isolation process requires a photolithography step and additional processing including a silicon etch step, an oxide deposition step, a planarization step, and possibly a thermal oxidation process to form a thermal oxide liner over the sidewalls and floor of the trench. Thus, it will be appreciated that the formation of adequate isolation structures in a typical semiconductor fabrication process can be an expensive, time consuming, and complicated process during which random defects in the form of particles may be generated possibly resulting in a decrease in the yield of the semiconductor process. In addition, the physical dimensions of the isolation structures places a lower limit on the density with which transistors may be fabricated on the substrate. In a LOCOS process, for example, it is well known that the thermal oxidation process that produces the field oxide structure is characterized by a bird's beak structure that laterally encroaches upon the active regions of the silicon substrate thereby increasing the minimum spacing between adjacent transistors. Shallow trench isolation dielectric structures also tend to result in some consumption of the active regions at the boundaries between the isolation regions and the active regions of the wafer. The surface area of the silicon substrate consumed by these isolation structures would be more desirably utilized as an active region of the circuit. Increased circuit density is desirable from a manufacturing perspective because of the increased number of devices that may be fabricated upon a single silicon wafer. In addition, smaller integrated circuits are less likely to be rendered non-functional by a randomly generated particle defect. In other words, smaller devices result in a larger number of devices available on a single wafer and in a higher manufacturing yield. Thus, it would be desirable to implement an MOS fabrication process that increased circuit density.
In addition to the density concerns described, conventional silicon fabrication processes typically result in source/drain interconnect structures that have a relatively high sheet resistivity. Typically, the source/drain regions of selected transistors are coupled to one another through a source/drain interconnect that is formed simultaneously with the formation of the transistor source/drain regions. Because these source/drain interconnects comprise doped silicon, their resistivity is typically higher than the resistivity associated with other well known materials used for interconnect structures in semiconductor fabrication process including, among others, aluminum, copper, and tungsten. The higher resistivity associated with source/drain interconnects may, in some circumstances, require the circuit designer to increase the physical dimensions of a source/drain interconnect to achieve a desired sheet resistivity. Under such circumstances, the larger physical dimensions imposed by the higher resistivity source/drain structure, may result in an additional reduction in the maximum circuit density attainable. Accordingly, it will be further desired to implement a semiconductor fabrication process in which the sheet resistivity of source/drain interconnects is less than the sheet resistivity of the heavily doped source/drain structures.